This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
このコースはFPGA Design for Embedded Systems専門講座に属します。
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FPGA Design for Embedded Systems専門講座コロラド大学ボルダー校（University of Colorado Boulder）このコースについて
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共有できる証明書
修了時に証明書を取得
100%オンライン
自分のスケジュールですぐに学習を始めてください。
次における4の2コース
中級レベル
約36時間で修了
英語
字幕：アラビア語, フランス語, ポルトガル語（ヨーロッパ）, イタリア語, ベトナム語, ドイツ語, ロシア語, 英語, スペイン語
習得するスキル
- Writing Code in Verilog
- Simulating FPGA Designs
- Designing FPGA Logic
- Designing Test Benches
- Writing code in VHDL
柔軟性のある期限
スケジュールに従って期限をリセットします。
共有できる証明書
修了時に証明書を取得
100%オンライン
自分のスケジュールですぐに学習を始めてください。
次における4の2コース
中級レベル
約36時間で修了
英語
字幕：アラビア語, フランス語, ポルトガル語（ヨーロッパ）, イタリア語, ベトナム語, ドイツ語, ロシア語, 英語, スペイン語
提供：
コロラド大学ボルダー校（University of Colorado Boulder）
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
修士号の取得を目指しましょう
この コース は コロラド大学ボルダー校（University of Colorado Boulder） の100%オンラインの Master of Science in Electrical Engineering の一部です。
プログラムのすべてで認定されれば、それらのコースが学位学習に加算されます。
シラバス - 本コースの学習内容
8時間で修了
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
8時間で修了
10件のビデオ （合計48分）, 3 学習用教材, 6 個のテスト
12時間で修了
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
12時間で修了
10件のビデオ （合計52分）, 2 学習用教材, 6 個のテスト
7時間で修了
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
7時間で修了
9件のビデオ （合計92分）, 2 学習用教材, 6 個のテスト
10時間で修了
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
10時間で修了
10件のビデオ （合計48分）, 2 学習用教材, 6 個のテスト
レビュー
- 5 stars58.70%
- 4 stars28.38%
- 3 stars6.88%
- 2 stars2.79%
- 1 star3.22%
HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN からの人気レビュー
MSにより2020年5月15日
This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
GMにより2021年8月26日
Excellent course! A broad review of several topics! Great videos and great assignments! I have been loving this specialization!
JSにより2021年6月6日
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
HHにより2020年5月14日
The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.
FPGA Design for Embedded Systems専門講座について
The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:
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