このコースについて
6,040 最近の表示

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自分のスケジュールですぐに学習を始めてください。

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スケジュールに従って期限をリセットします。

中級レベル

約12時間で修了

英語

字幕:英語

100%オンライン

自分のスケジュールですぐに学習を始めてください。

柔軟性のある期限

スケジュールに従って期限をリセットします。

中級レベル

約12時間で修了

英語

字幕:英語

シラバス - 本コースの学習内容

1
1時間で修了

Orientation

In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course....
2件のビデオ (合計23分), 2 readings, 1 quiz
2件のビデオ
Two Tools Tutorial4 分
2件の学習用教材
Syllabus10 分
Tools For This Course10 分
1の練習問題
Demographics Survey5 分
3時間で修了

ASIC Placement

In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks....
9件のビデオ (合計163分), 2 readings
9件のビデオ
Basics17 分
Wirelength Estimation15 分
Simple Iterative Improvement Placement12 分
Iterative Improvement with Hill Climbing15 分
Simulated Annealing Placement27 分
Analytical Placement: Quadratic Wirelength Model14 分
Analytical Placement: Quadratic Placement26 分
Analytical Placement: Recursive Partitioning18 分
Analytical Placement: Recursive Partitioning Example16 分
2件の学習用教材
Week 1 Overview10 分
Week 1 Assignments10 分
2
6時間で修了

Technology Mapping

Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD....
6件のビデオ (合計102分), 2 readings, 2 quizzes
6件のビデオ
Technology Mapping as Tree Covering29 分
Technology Mapping—Tree-ifying the Netlist13 分
Technology Mapping—Recursive Matching9 分
Technology Mapping—Minimum Cost Covering16 分
Technology Mapping—Detailed Covering Example14 分
2件の学習用教材
Week 2 Overview10 分
Week 2 Assignments10 分
1の練習問題
Problem Set #1
3
4時間で修了

ASIC Routing

Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment....
9件のビデオ (合計145分), 2 readings, 1 quiz
9件のビデオ
Maze Routing: 2-Point Nets in 1 Layer16 分
Maze Routing: Multi-Point Nets12 分
Maze Routing: Multi-Layer Routing12 分
Maze Routing: Non-Uniform Grid Costs14 分
Implementation Mechanics: How Expansion Works23 分
Implementation Mechanics: Data Structures & Constraints18 分
Implementation Mechanics: Depth First Search14 分
From Detailed Routing to Global Routing15 分
2件の学習用教材
Week 3 Overview10 分
Week 3 Assignments10 分
1の練習問題
Problem Set #2
4
7時間で修了

Timing Analysis

You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design....
8件のビデオ (合計148分), 2 readings, 2 quizzes
8件のビデオ
Basics7 分
Logic-Level Timing: Basic Assumptions & Models30 分
Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks27 分
Logic-Level Timing: A Detailed Example and the Role of Slack10 分
Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths26 分
Interconnect Timing: Electrical Models of Wire Delay16 分
Interconnect Timing: The Elmore Delay Model14 分
Interconnect Timing: Elmore Delay Examples14 分
2件の学習用教材
Week 4 Overview10 分
Week 4 Assignments10 分
1の練習問題
Problem Set #3
4.8
15件のレビューChevron Right

人気のレビュー

by ALOct 21st 2018

Great basic overview of the core design principles for EDA

講師

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Rob A. Rutenbar

Adjunct Professor
Department of Computer Science

イリノイ大学アーバナ・シャンペーン校(University of Illinois at Urbana-Champaign)について

The University of Illinois at Urbana-Champaign is a world leader in research, teaching and public engagement, distinguished by the breadth of its programs, broad academic excellence, and internationally renowned faculty and alumni. Illinois serves the world by creating knowledge, preparing students for lives of impact, and finding solutions to critical societal needs. ...

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