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VLSI CAD Part II: Layout に戻る

イリノイ大学アーバナ・シャンペーン校(University of Illinois at Urbana-Champaign) による VLSI CAD Part II: Layout の受講者のレビューおよびフィードバック

4.8
262件の評価

コースについて

You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class)....

人気のレビュー

NS

2020年6月15日

This course is good for anyone who wants himself in the EDA industry. The teacher is very passionate and engaging, the content is thorough and well prepared.

MM

2020年5月13日

It was a great course, I learned a lot of new things from it. And the presentation and explanation of concepts by Prof. Rob A. Rutenbar were amazing!!!

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VLSI CAD Part II: Layout: 26 - 49 / 49 レビュー

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